1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device provided with data transmission lines.
2. Description of the Related Art
In general, a semiconductor memory device is classified into a volatile memory device or a nonvolatile memory device. Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) are representative volatile memory devices. Programmable Read Only Memory (PROM), Erasable PROM (EPROM), Electrically EPROM (EEPROM), and flash memory device are nonvolatile memory devices. The most important characteristic for distinguishing the volatile memory device from the nonvolatile memory device is whether data stored in a memory cell is retained in a non-powered condition.
In other words, in the volatile memory device, the data stored in the memory cell is not retained in a non-powered condition, while in the nonvolatile memory device, the data stored in the memory cell is retained in a non-powered condition. Especially, in the case of DRAM, a refresh operation is necessary in order to retain data, and such a refresh operation is not necessary in the non-volatile memory device. Since such a characteristic of the non-volatile memory device is suitable for low power and high integration, the non-volatile memory device has been extensively used as a storage medium of a portable apparatus in recent years.
FIG. 1 is a diagram for explaining an internal configuration of a conventional semiconductor memory device. For the convenience of description, a configuration corresponding to one memory bank 110 will be described as an example.
Referring to FIG. 1, the semiconductor memory device includes the memory bank 110, a plurality of buffers PB[0:7] arranged in a buffer area 120, and a plurality of column selection units CS[0:4K−1].
The memory bank 110 is configured to store desired data, and be accessed in response to an address (not illustrated) that includes predetermined number of bits. Each of the buffers PB[0:7] stores data, which are stored in a plurality of memory cells in a read operation, and transfers the stored data to bit lines BL[0:7] and bit bar lines /BL[0:7] in response to activated one of a plurality of selection signals S[0:4K−1]. The plurality of column selection units CS[0:4K−1] decode input addresses and activate a corresponding selection signal based on the decoded input addresses.
Hereinafter, a read operation of the semiconductor memory device will be described.
First, in the read operation, the data stored in the memory bank 110 are loaded to the plurality of buffers PB[0:7]. The plurality of column selection units CS[0:4K−1] activate one of the plurality of selection signals S[0:4K−1] in response to the input addresses, and corresponding buffers are activated in response to the activated selection signal. Then, data stored in the activated buffers are transferred to the bit lines BL[0:7] and the bit bar lines /BL[0:7]. The transferred data is amplified and output by a sense amplifier (not illustrated).
FIG. 2 is a circuit diagram for explaining a detailed structure of the plurality of buffers PB[0:7] of FIG. 1.
For reference, a group of the buffers PB[0], which is coupled to a 0th bit line BL[0] and a 0th bit bar line /BL[0], is referred to as a 0th buffering unit 200.
Referring to FIG. 2, a buffer PB[0] of the 0th buffering unit 200, which is activated in response to a 0th selection signal S[0], includes a latching section 210 for storing data in response to a control signal (not illustrated) and a transfer section 220 for transferring the data stored in the latching section 210 to the 0th bit line BL[0] and the 0th bit bar line /BL[0] in response to the 0th selection signal S[0]. The activation of the buffer PB[0] in response to the 0th selection signal S[0] represents that an NMOS transistor of the transfer section 220 is turned on in response to the 0th selection signal S[0], and the data stored in the latching section 210 is transferred to the 0th bit line BL[0] and the 0th bit bar line /BL[0].
Meanwhile, in a conventional structure, the 0th bit line BL[0] and the 0th bit bar line /BL[0] are connected to the plurality of buffers PB[0] of the 0th buffering unit 200. That is, junction capacitance of all transistors connected to a corresponding bit line is reflected in the 0th bit line BL[0] and the 0th bit bar line /BL[0]. In other words, capacitance of the 0th bit line BL[0] and the 0th bit bar line /BL[0] are obtained by adding junction capacitance of 8K transistors to self-capacitance of the 0th bit line BL[0] and the 0th bit bar line /BL[0], which correspond to a length LOB of the 0th buffering unit 200, where two transistors are connected to each other per one buffer. The length LOB of the 0th buffering unit 200 represents a length corresponding to the buffer area 120 (referring to FIG. 1). In other words, the length LOB of the 0th buffering unit represents a length corresponding to the number of the buffers PB[0] provided in the 0th buffering unit 200. In FIG. 2, since the number of the buffers PB[0] provided the 0th buffering unit 200 is 4K, the 0th bit line BL[0] and the 0th bit bar line /BL[0] have lengths corresponding to 4K buffers.
The aforementioned capacitance of the 0th bit line BL[0] and the 0th bit bar line /BL[0] are reflected in other bit lines and bit bar lines in the same manner, other than the 0th bit line BL[0] and the 0th bit bar line /BL[0]. Here, an increase in the capacitance reflected in the bit line and the bit bar line represents an increase in a time for precharging the bit line and the bit bar line, and thus, represents an increase in a time for sensing data transferred through the bit line and the bit bar line. Therefore, the increase in the time for sensing the data may reduce a data processing speed of the semiconductor memory device.